论文
7.4 A 0.027mm<sup>2</sup> 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fs<sub>rms</sub> Jitter and -74.2dBc Reference Spur
期刊: 2024 IEEE International Solid-State Circuits Conference (ISSCC) 2024作者: Yunbo Huang,Yong Chen,Zunsong Yang,Rui P. Martins,Pui-In Mak
DOI:10.1109/isscc49657.2024.10454291
A 6-GHz 78-fs$_{\mathrm{RMS}}$ Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving $-$92-dBc Reference Spur and $-$258-dB FOM
期刊: IEEE Microwave and Wireless Technology Letters 2024作者: Hongyu Ren,Zunsong Yang,Yunbo Huang,Chaoping Feng,Tianle Chen,Xinming Zhang,Xianghe Meng,Weiwei Yan,Weidong Zhang,Tetsuya Iizuka,Yong Chen,Pui-In Mak,Zhengsheng Han,Bo Li
DOI:10.1109/lmwt.2024.3377117
A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving −80-dBc Reference Spur and −259-dB FoM with 12-pF Input Load
期刊: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 2023作者: Zunsong Yang,Masaru Osada,Shuowei Li,Yuyang Zhu,Tetsuya Iizuka
DOI:10.23919/vlsitechnologyandcir57934.2023.10185259
Power-Efficient RF and mm-Wave VCOs/PLL
期刊: Analog Circuits and Signal Processing 2023作者: Hao Guo,Zunsong Yang,Chee Cheow Lim,Harikrishnan Ramiah,Yatao Peng,Yong Chen,Jun Yin,Pui-In Mak,Rui P. Martins
DOI:10.1007/978-3-031-22231-3_2
Investigation and Improvement on Self-dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis
期刊: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2023作者: Yuyang Zhu,Zunsong Yang,Masaru Osada,Haoming Zhang,Tetsuya Iizuka
DOI:10.1587/transfun.2023gcl0002
A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit
期刊: 2023 International Conference on IC Design and Technology (ICICDT) 2023作者: Yuyang Zhu,Zunsong Yang,Zhenyu Cheng,Md Shamim Sarker,Hiroyasu Yamahara,Munetoshi Seki,Hitoshi Tabata,Tetsuya Iizuka
DOI:10.1109/icicdt59917.2023.10332304
Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit
期刊: 2023 International Conference on IC Design and Technology (ICICDT) 2023作者: Zhenyu Cheng,Zunsong Yang,Yuyang Zhu,Md Shamim Sarker,Hiroyasu Yamahara,Munetoshi Seki,Hitoshi Tabata,Tetsuya Iizuka
DOI:10.1109/icicdt59917.2023.10332416
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM
期刊: IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2022作者: Zunsong Yang,Yong Chen,Jia Yuan,Pui-In Mak,Rui P. Martins
DOI:10.1109/tvlsi.2021.3131219
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving −63-dBc Reference Spur, 175-fs RMS Jitter and −240-dB FOMjitter
期刊: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 2022作者: Zunsong Yang,Zule Xu,Masaru Osada,Tetsuya Iizuka
DOI:10.1109/vlsitechnologyandcir46769.2022.9830382
A 0.003-mm<sup>2</sup> 440fs<sub>RMS</sub>-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS
期刊: IEEE Transactions on Circuits and Systems I: Regular Papers 2021作者: Zunsong Yang,Yong Chen,Pui-In Mak,Rui P. Martins
DOI:10.1109/tcsi.2021.3065462
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector
期刊: IEEE Access 2020作者: Zunsong Yang,Yong Chen,Shiheng Yang,Pui-In Mak,Rui P. Martins
DOI:10.1109/access.2019.2962060
A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL With −78.7-dBc REF Spur, −128.1-dBc/Hz Absolute In-Band PN and −254-dB FOM
期刊: IEEE Solid-State Circuits Letters 2020作者: Zunsong Yang,Yong Chen,Pui-In Mak,Rui P. Martins
DOI:10.1109/lssc.2020.3031901
16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur
期刊: 2019 IEEE International Solid- State Circuits Conference - (ISSCC) 2019作者: Zunsong Yang,Yong Chen,Shiheng Yang,Pui-In Mak,Rui P. Martins
DOI:10.1109/isscc.2019.8662364
A 0.0071-mm<sup>2</sup> 10.8ps<sub>pp</sub>-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis
期刊: IEEE Transactions on Circuits and Systems I: Regular Papers 2019作者: Yong Chen,Pui-In Mak,Zunsong Yang,Chirn Chye Boon,Rui P. Martins
DOI:10.1109/tcsi.2019.2919623
A 0.003-mm<sup>2</sup> 440fs<sub>RMS</sub>-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS
期刊: 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC) 2019作者: Zunsong Yang,Yong Chen,Pui-In Mak,Rui P. Martins
DOI:10.1109/a-sscc47793.2019.9056944
A $6.5\times7\,\mu$ m<sup>2</sup> 0.98-to-1.5 mW Nonself-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4–44 GHz)
期刊: IEEE Solid-State Circuits Letters 2019作者: Yong Chen,Zunsong Yang,Xiaoteng Zhao,Yunbo Huang,Pui-In Mak,Rui P. Martins
DOI:10.1109/lssc.2019.2920226
